Trellis Intellectual Property Law Group, PC

Education

B.S.	Louisiana State University, Baton Rouge, LA, 1989 Electrical Engineering Minor in Mathematics
M.S.	Rice University, Houston, TX, 1993 Master of Electrical Engineering Focus in Computer Engineering
J.D.	Santa Clara University, Santa Clara, CA, 2005 High Technology Law Certificate

Bar Memberships

2006 California

Professional Employment

Trellis Intellectual Property Law Group, PC, Palo Alto, CA, 2007

Patent attorney

Patent agent, 2003 to 2006

Patent prosecution: prepare patent applications and office action responses.

Cypress Semiconductor, San Jose, CA, 2001 to 2003

Patent Agent

Prepared provisional applications, reviewed applications and office action responses, performed patent analysis projects, and supported internal patent committee process.

Lara Networks, San Jose, CA, 2000 to 2001 (Acquired by Cypress)

Manager, Circuit Design

Led design teams in CAM-based hardware search engine development. Patents: 6,988,164; 6,845,024; and 6,954,823.

Vanguard International Semiconductor, San Jose, CA, 1996-2000

Project Manager

Hands-on project management with full project responsibility: team direction, project planning, circuit design, chip planning, scheduling, simulation, layout, verification, plot-checking, tape-out, engineering debug, and revisions. 128/144Mb Direct Rambus RDRAM Project Manager (0.19um technology): Led a team of up to 20 people and executed the project on schedule. 16Mb (x8/x16) SDRAM Project Manager (0.35um technology): Led a team of up to 7 people and executed the project on schedule. Patents: 5,796,665; 5,999,477; 6,016,072; 6,018,489; 6,052,328; 6,060,873; 6,061,296; 6,208,197; 6,246,619; and 6,764,867.

Alliance Semiconductor, San Jose, CA, 1995 to 1996

Senior Design Engineer

Synchronous Burst SRAM (32Kx32) design and project leader. Responsible for all circuit design, layout, mask-making, and test/debug support. Met all project schedules and reached production in 0.45um technology process. Patents: 5,517,137; 5,548,560; 5,550,500; 5,550,783 and 5,559,752.

Intel, Portland, OR, 1994 to 1995

Design Engineer

Microprocessor cache SRAM circuit design (P6 project, L2 cache).

Texas Instruments, Houston, TX, 1990 to 1994